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EL7562
May 1, 2006 FN7295.1
Monolithic 2Amp DC-DC Step-Down Regulator
The EL7562 is an integrated, synchronous step-down regulator with output voltage adjustable from 1.0V to 3.8V. It is capable of delivering 2A continuous current at up to 95% efficiency. The EL7562 operates at a constant frequency pulse width modulation (PWM) mode, making external synchronization possible. Patented on-chip resistorless current sensing enables current mode control, which provides cycle-by-cycle current limiting, over-current protection, and excellent step load response. The EL7562 is available in a fused-lead 16 Ld QSOP package. With proper external components, the whole converter fits into a less than 0.5 in2 area. The minimal external components and small size make this EL7562 ideal for desktop and portable applications. The EL7562 is specified for operation over the 0C to +70C temperature range.
Features
* Integrated synchronous MOSFETs and current mode controller * 2A continuous output current * Up to 95% efficiency * 3.3V or 5V nominal input voltage * Adjustable output from 1V to 3.8V * Cycle-by-cycle current limit * Precision reference * 0.5% load and line regulation * Adjustable switching frequency to 1MHz * Oscillator synchronization possible * Internal soft-start * Over-temperature protection * Under-voltage lockout * 16 Ld QSOP package
Pinout
EL7562 (16 LD QSOP) TOP VIEW
* Pb-free plus anneal available (RoHS compliant)
Applications
* DSP, CPU core and IO supplies * Logic/Bus supplies
C3 R3
C4
1 SGND 2 COSC 3 VDD
PGND 16 C5 VREF 15 0.1F R2 FB 14 VDRV 13 LX 12 LX 11 VHI 10 C6 0.1F R1 2.37k 1k VO (3.3V, 2A) 100F
* Portable equipment * DC-DC converter modules * GTL + Bus power supply
0.1F 270pF
39 4 PGND C1 100F C2 0.1F 5 PGND 6 VIN 7 VIN VIN (4.5V- 5.5V) 8 EN
Ordering Information
C7
PART NUMBER EL7562CU EL7562CU-T7
PART TAPE & MARKING REEL 7562CU 7562CU 7562CU 7562CUZ 7562CUZ 7" 13" 7" 13"
PACKAGE
PKG. DWG. #
16 Ld QSOP MDP0040 16 Ld QSOP MDP0040 16 Ld QSOP MDP0040 16 Ld QSOP MDP0040 (Pb-free) 16 Ld QSOP MDP0040 (Pb-free) 16 Ld QSOP MDP0040 (Pb-free)
PGND 9
EL7562CU-T13 EL7562CUZ (Note) EL7562CUZ-T7 (Note)
Please refer to page 4 for 3.3V input Application Diagram Manufactured under U.S. Patent No. 57,323,974
EL7562CUZ-T13 7562CUZ (Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VIN or VDD and GND . . . . . . . . . . . . +6.5V VLX Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN +0.3V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, VDD +0.3V VHI Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V, VLX +6V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Operating Ambient Temperature . . . . . . . . . . . . . . . . . 0C to +70C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER VREF VREFTC VREFLOAD VRAMP IOSC_CHG IOSC_DIS IVDD+VDRV IVDD_OFF VDD_OFF VDD_ON TOT THYS ILEAK ILMAX RDSON RDSONTC VFB VFB_LINE VFB_LOAD VFB_TC IFB VEN_HI VEN_LO IEN Reference Accuracy
VDD = VIN = 5V, TA = TJ = 25C, COSC = 270pF, unless otherwise specified. CONDITIONS MIN 1.24 TYP 1.26 50 0 < IREF < 50A -1 1.15 0.1V < VOSC < 1.25V 0.1V < VOSC < 1.25V VEN = 4V, FOSC = 120kHz EN = 0 2.5 2.6 135 20 EN = 0, LX = 5V (low FET), LX = 0V (high FET) 3 Wafer level test only 60 0.2 ILOAD = 0A VIN = 5V, VIN = 10%, ILOAD = 0A 0.1A < ILOAD < 1A -40C < TA < 85C, ILOAD = 0.5A VFB = 0V (Note) 4 1 VEN = 0 -4 -2.5 0.970 0.985 0.5 0.5 1 100 200 1.000 120 20 2 1 200 8 6.5 1.5 2.7 3 MAX 1.28 UNIT V ppm/C % V A mA mA mA V V C C A A m m/C V % % % nA V V A
DESCRIPTION
Reference Temperature Coefficient Reference Load Regulation Oscillator Ramp Amplitude Oscillator Charge Current Oscillator Discharge Current VDD+VDRV Supply Current VDD Standby Current VDD for Shutdown VDD for Startup Over-temperature Threshold Over-temperature Hysteresis Internal FET Leakage Current Peak Current Limit FET On Resistance RDSON Tempco Output Initial Accuracy Output Line Regulation Output Load Regulation Output Temperature Stability Feedback Input Pull Up Current EN Input High Level EN Input Low Level Enable Pull Up Current
NOTE: VEN_HI is typically 2/3 of VDD. For VDD = 3.3V, VEN_HI is 2.2V typical.
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Closed-Loop AC Electrical Specifications
PARAMETER FOSC tSYNC MSS tBRM tLEB DMAX DESCRIPTION Oscillator Initial Accuracy Minimum Oscillator Sync Width Soft-start Slope FET Break Before Make Delay High Side FET Minimum On Time Maximum Duty Cycle
VS = VIN = 5V, TA = TJ = 25C, COSC = 270pF, unless otherwise specified. CONDITIONS MIN 493 TYP 580 25 0.5 15 150 95 MAX 667 UNIT kHz ns V/ms ns ns %
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN NAME SGND COSC VDD PGND PGND VIN VIN EN PGND VHI LX LX VDRV FB VREF PGND Control circuit negative supply Oscillator timing capacitor; FOSC can be approximated by: FOSC (kHz) = 0.1843/COSC, COSC in F Control circuit positive supply Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET Power supply input of the regulator; connected to the drain of the high-side NMOS power FET Power supply input of the regulator; connected to the drain of the high-side NMOS power FET Chip enable, active high; a 2A internal pull-up current enables the device if the pin is left open Ground return of the regulator Positive supply of the high-side driver Inductor drive pin; high current digital output whose average voltage equals the regulator output voltage Inductor drive pin; high current digital output whose average voltage equals the regulator output voltage Positive supply of the low-side driver and input voltage for the high-side boot strap Voltage feedback input; connected to an external resistor divider between VOUT and GND; a 125nA pull-up current forces VOUT to VS in the event that FB is floating Bandgap reference bypass capacitor; typically 0.1F to GND Ground return of the regulator PIN FUNCTION
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Application Diagram for 3.3V Input
C3 0.1F R3
C4 270pF
1 SGND 2 COSC 3 VDD
PGND 16 C5 VREF 15 0.1F FB 14 VDRV 13 C8 C9 0.1F L1 VO (2.5V, 2A) C7 100F R2 1.54k R1 1k LX 12 LX 11 VHI 10 PGND 9 0.1F D2 D3 D4
39 4 PGND 5 PGND 6 VIN 7 VIN VIN (3V-3.6V) 8 EN
C1 100F
C2 0.1F
C6 0.1F
4.7F
EL7562 (16 Ld QSOP)
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Typical Performance Curves
Efficiency vs IO VIN=5V 100 95 90 85 80 75 70 65 60 0.1 FS=500kH L=Coilcraft DO3316P0 1 LOAD CURRENT IO (A) Efficiency vs IO VO=3.3V 100 95 90 Efficiency (%) 85 80 75 70 65 60 0 0.5 1 LOAD CURRENT IO (A) Line Regulation VO=3.3V 0.6 0.4 IO=0.1A 0.2 0 -0.2 -0.4 -0.6 4.5 IO=1A IO=2A VREF (V) VO (%) 1.258 1.256 1.254 1.252 1.25 1.248 1.246 1.244 1.242 4.7 4.9 VIN (V) 5.1 5.3 5.5 0 10 20 30 40 50 60 70 80 90 100 110 TEMPERATURE (C) 1.5 2 VIN=4.5 0.6 Output Voltage (%) VIN=5V VIN=5.5 0.4 0.2 0 -0.2 -0.4 -0.6 0 0.5 1 LOAD CURRENT IO (A) VREF vs Temperature 1.5 2 VIN=4.5 VIN=5.5 0.8 2 0 0.5 1 LOAD CURRENT IO (A) Load Current IO (A) Load Regulation VO=3.3V 1.5 2 VO=1.8 Power Loss (W) Efficiency (%) VO=2.5 VO=3.3 0.7 0.6 0.5 0.4 0.3 0.2 0.1 VO=1.5 VO=1.8 VO=1.2 VO=2.5 VO=3.3 Power Loss vs IO VIN=5V
VO=1.5
VO=1.2
VIN=5V
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Typical Performance Curves
(Continued)
Oscillator Frequency vs Temperature 390 COSC=390p Oscillator Frequency (kHz) 385 380 375 370 365 360 0 10 20 30 40 50 60 70 80 90 100 110 TEMPERATURE (C) Input Current (A) 0.94 0.92 0.9 0.96
Input Current vs Temperature (Enable connected to GND) VIN=5.5
VIN=5V VIN=4.5
0.88 0.86 0.84 0.82 0.8 0 10 20 30 40 50 60 70 80 90 100 110 TEMPERATURE (C)
Switching Frequency vs COSC 1400 1200 1000 FS (kHz) 800 600 400 200 0 0 200 400 600 800 1000 COSC (pF)
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Block Diagram
0.1F 270pF
VREF Junction Temperature Voltage Reference
COSC VDRV
Oscillator
Controller Supply 39 VDD
VHI VIN
5V
0.1F PWM Controlle Drivers
Power FET Power FET
0.1F 4.7H VOUT 100F PGND 2370
EN
1k
Current Sense
SGND
FB
Applications Information
Circuit Description General
The EL7562 is a fixed frequency, current mode controlled DC-DC converter with integrated N-channel power MOSFETs and a high precision reference. The device incorporates all the active circuitry required to implement a cost effective, user-programmable 2A synchronous stepdown regulator suitable for use in DSP core power supplies.
Theory of Operation
The EL7562 is composed of 5 major blocks: 1. PWM Controller 2. NMOS Power FETs and Drive Circuitry 3. Bandgap Reference 4. Oscillator 5. Thermal Shut-down
PWM Controller
The EL7562 regulates output voltage through the use of current-mode controlled pulse width modulation. The three main elements in a PWM controller are the feedback loop and reference, a pulse width modulator whose duty cycle is controlled by the feedback error signal, and a filter which
averages the logic level modulator output. In a step-down (buck) converter, the feedback loop forces the timeaveraged output of the modulator to equal the desired output voltage. Unlike pure voltage-mode control systems, currentmode control utilizes dual feedback loops to provide both output voltage and inductor current information to the controller. The voltage loop minimizes DC and transient errors in the output voltage by adjusting the PWM duty-cycle in response to changes in line or load conditions. Since the output voltage is equal to the time-averaged of the modulator output, the relatively large LC time constant found in power supply applications generally results in low bandwidth and poor transient response. By directly monitoring changes in inductor current via a series sense resistor the controller's response time is not entirely limited by the output LC filter and can react more quickly to changes in line and load conditions. This feed-forward characteristic also simplifies AC loop compensation since it adds a zero to the overall loop response. Through proper selection of the currentfeedback to voltage-feedback ratio the overall loop response will approach a one-pole system. The resulting system offers several advantages over traditional voltage control systems, including simpler loop compensation, pulse by pulse current limiting, rapid response to line variation and good load step response.
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The heart of the controller is an input direct summing comparator which sum voltage feedback, current feedback, slope compensation ramp and power tracking signals together. Slope compensation is required to prevent system instability that occurs in current-mode topologies operating at duty-cycles greater than 50% and is also used to define the open-loop gain of the overall system. The slope compensation is fixed internally and optimized for 500mA inductor ripple current. The power tracking will not contribute any input to the comparator steady-state operation. Current feedback is measured by the patented sensing scheme that senses the inductor current flowing through the high-side switch whenever it is conducting. At the beginning of each oscillator period the high-side NMOS switch is turned on. The comparator inputs are gated off for a minimum period of time of about 150ns (LEB) after the high-side switch is turned on to allow the system to settle. The Leading Edge Blanking (LEB) period prevents the detection of erroneous voltages at the comparator inputs due to switching noise. If the inductor current exceeds the maximum current limit (ILMAX) a secondary over-current comparator will terminate the high-side switch on time. If ILMAX has not been reached, the feedback voltage FB derived from the regulator output voltage VOUT is then compared to the internal feedback reference voltage. The resultant error voltage is summed with the current feedback and slope compensation ramp. The high-side switch remains on until all four comparator inputs have summed to zero, at which time the high-side switch is turned off and the low-side switch is turned on. However, the maximum on-duty ratio of the high-side switch is limited to 95%. In order to eliminate cross-conduction of the high-side and low-side switches a 15ns break-beforemake delay is incorporated in the switch drive circuitry. The output enable (EN) input allows the regulator output to be disabled by an external logic control signal.
NMOS Power FETs and Drive Circuitry
The EL7562 integrates low on-resistance (60m) NMOS FETs to achieve high efficiency at 2A. In order to use an NMOS switch for the high-side drive it is necessary to drive the gate voltage above the source voltage (LX). This is accomplished by bootstrapping the VHI pin above the LX voltage with an external capacitor CVHI and internal switch and diode. When the low-side switch is turned on and the LX voltage is close to GND potential, capacitor CVHI is charged through internal switch to VDRV, typically 5V. At the beginning of the next cycle the high-side switch turns on and the LX pins begin to rise from GND to VIN potential. As the LX pin rises the positive plate of capacitor CVHI follows and eventually reaches a value of VDRV+VIN, typically 10V, for VDRV=VIN=5V. This voltage is then level shifted and used to drive the gate of the high-side FET, via the VHI pin. A value of 0.1F for CVHI is recommended.
Reference
A 1.5% temperature compensated bandgap reference is integrated in the EL7562. The external VREF capacitor acts as the dominant pole of the amplifier and can be increased in size to maximize transient noise rejection. A value of 0.1F is recommended.
Oscillator
The system clock is generated by an internal relaxation oscillator with a maximum duty-cycle of approximately 95%. Operating frequency can be adjusted through the COSC pin or can be driven by an external source. If the oscillator is driven by an external source care must be taken in selecting the ramp amplitude. Since CSLOPE value is derived from the COSC ramp, changes to COSC ramp will change the CSLOPE compensation ramp which determine the open-loop gain of the system. When external synchronization is required, always choose COSC such that the free-running frequency is at least 20% lower than that of sync source to accommodate component and temperature variations. Figure 1 shows a typical connection.
1 100p BAT54 2 3 6 7 8 EL7562 15 14 11 10 9 16
Output Voltage Setting
In general:
R 2 V OUT = 0.985 x 1 + ------ R 1
For VIN = 5V
R 2 V OUT = 0.975 x 1 + ------ R 1
FOR VIN = 3.3V
External Oscillato
However, due to the relatively low open loop gain of the system, gain errors will occur as the output voltage and loopgain is changed. This is shown in the performance curves. A 100nA pull-up current from FB to VDD forces VOUT to GND in the event that FB is floating.
FIGURE 1. OSCILLATOR SYNCHRONIZATION
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Thermal Shut-down
An internal temperature sensor continuously monitors die temperature. In the event that die temperature exceeds the thermal trip-point, the system is in fault state and will be shut down. The upper and low trip-points are set to 135C and 115C respectively.
The demo board is a good example of layout based on these principles. Please refer to the EL7562 Application Brief for the layout.
Start-up Delay
A capacitor can be added to the EN pin to delay the converter start-up (Figure 2) by utilizing the pull-up current. The delay time is approximately:
t d ( ms ) = 1200 x C ( F )
1 2 3 6 7 8 C EL7562
1 1 1 1 1 9 TIME td VOU VIN VO
FIGURE 2. START-UP DELAY
Layout Considerations
The layout is very important for the converter to function properly. Power Ground ( ) and Signal Ground (--) should be separated to ensure that the high pulse current in the Power Ground never interferes with the sensitive signals connected to Signal Ground. They should only be connected at one point (normally at the negative side of either the input or output capacitor). The trace connected to pin 14 (FB) is the most sensitive trace. It needs to be as short as possible and in a "quiet" place, preferably between PGND or SGND traces. In addition, the bypass capacitor connected to the VDD pin needs to be as close to the pin as possible. The heat of the chip is mainly dissipated through the PGND pins. Maximizing the copper area around these pins is preferable. In addition, a solid ground plane is always helpful for the EMI performance.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9

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